1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising a memory cell for reading and writing data, more particularly, to a technology for optimizing a timing of a controlling signal which controls an internal circuit.
The present invention relates to a semiconductor integrated circuit having a testing mode, more particularly, to a technology for modifying an operation timing of an internal circuit in a testing mode.
2. Description of the Related Art
Integration levels and operation speeds of semiconductor integrated circuits such as microcomputers and DRAM's have been improving. Recently, timing margins of controlling signals used in internal circuits have been reduced due to the increasing operation speeds, and timing design considering wiring length or the like within a chip has been carried out.
FIG. 1 shows a chip layout of an SDRAM (Synchronous DRAM) among semiconductor integrated circuits of this kind, which operates in synchronization with a clock signal. FIG. 1 shows circuits related to data input/output in accordance with a column address.
An SDRAM 1 comprises four pairs of memory core units 2 laid out in mirror symmetry in each of the pairs. A peripheral circuit 3 (the stippled portion in FIG. 1) is arranged at the center of the SDRAM 1 in a cross-like shape along the vertical and horizontal directions of the SDRAM 1.
Each of the memory core units 2 comprises a plurality of main-decoders 4, sense amplifiers 5, switching circuits 6, memory cells 7, sense buffers 8, and write amplifiers 9. (Hereinafter, explanation of the plurality of the circuits above and a pad described below will be given for each single unit of the circuits, such as "the sense amplifier 5" instead of "each of the sense amplifiers 5", except for some cases of the sense buffers 8 and the write amplifiers 9 where each buffer or amplifier is specified by a reference code.) A pre-decoder 10 is arranged between each pair of the memory core units 2 laid out in mirror symmetry.
Pads 11 for receiving and transmitting signals from and to the exterior of the chip are arranged within the peripheral circuit 3 along the horizontal direction of FIG. 1. wirings of a read data signal RDBZ, a write data signal WDBZ, testing read data signals TRDBZ and TRDBX, and a testing write data signal TWDBZ is arranged within the peripheral circuit 3 along the horizontal direction of FIG. 1. The peripheral circuit 3 comprises a data input/output circuit 12, a clock buffer 13, a clock pulse generator 14, a timing controlling circuit 15, a resetting circuit 16, a testing circuit 17, a controlling circuit 18, or the like.
The clock buffer 13 receives a clock signal CLK from the exterior through the pad 11, and outputs an internal clock signal CLKZ. The clock pulse generator 14 receives the internal clock signal CLKZ and outputs a clock pulse signal CEPZ. The timing controlling circuit 15 receives the clock pulse signal CEPZ and outputs a read controlling signal SEBZ and a write controlling signal WAEZ. The resetting circuit 16 receives the read controlling signal SEBZ, the read data signal RDBZ, and the testing read data signals TRDBZ and TRDBX. The data input/output circuit 12 receives the read data signal RDBZ, the write data signal WDBZ, the testing read data signals TRDBZ and TRDBX and the testing write data signal TWDBZ. The data input/output circuit 12 also receives a data signal DQ through the pad 11. The testing circuit 17 outputs a testing signal TESZ. The testing signal TESZ is supplied to the data input/output circuit 12, the resetting circuit 16, the sense amplifier 8, and the write amplifier 9, which is not shown in FIG. 1.
The pre-decoder 10 receives the clock pulse signal CEPZ and a row address signal which is not shown in FIG. 1. The pre-decoder 10 outputs a column decoding signal CAZ to the main-decoder 4. A portion of wiring of the clock pulse signal CEPZ is formed horizontally along the memory core unit 2, and wiring length thereof is long. Therefore, a load of the wiring of the clock pulse signal CEPZ is large. Likewise, wiring of the column decoding signal CAZ is formed vertically within the main-decoder 4, and has long length. Therefore, a load of the wiring of the column decoding signal is also large.
The main-decoder 4 receives the column decoding signal CAZ and outputs a column selecting signal CLZ. The sense amplifier 5 receives bit line signals BLX and BLZ. The bit line signals BLX and BLZ are complementary signals.
The memory cell 7 receives the bit line signals BLX and BLZ. The switching circuit 6 receives the column selecting signal CLZ, the bit line signals BLX and BLZ and internal data signals GDBZ and GDBX. The sense buffer 8 receives the internal data signals GDBZ and GDBX and outputs the read data signal RDBZ and the testing read data signals TRDBZ and TRDBX. The write amplifier 9 receives the write data signal WDBZ and the testing write data signal TWDB, and outputs the internal data signals GDBZ and GDBX.
A J-shaped arrow A1 shown in the memory core unit 2 in FIG. 1 means that data read from the memory cell 7 are amplified by the sense amplifier 5 as the bit line signals BLZ and BLX and supplied to the sense buffer 8 through the switching circuit 6. A J-shaped arrow A2 means that write data output from the write amplifier 9 through the switching circuit 6 is supplied to the sense amplifier 5 as the bit line signals BLZ and BLX and written to the memory cell 7.
Each signal line described above is also connected to the pre-decoders 10 and to the memory core units 2 where the signal lines are not shown in FIG. 1.
Each signal line or wiring shown by a thick line in FIG. 1 comprises a plurality of lines. For example, the read data signal RDBZ comprises read data signals RDB0Z, RDB1Z, RDB2Z, and RDB3Z, and the write data signal WDBZ comprises write data signals WDB0Z, WDB1Z, WDB2Z, and WDB3Z.
The signals suffixed with "Z" mean signals of positive logic, while the signals suffixed with "X" are signals of negative logic.
FIG. 2 shows main circuits and flow of main signals which are related to a column address.
The switching circuit 6 comprises an nMOS transistor. The gate of the nMOS transistor receives the column selecting signal CLZ and the source and the drain thereof receive the bit line signals BLZ and BLX and the internal data signals GDBZ and GDBX, respectively. Hereinafter, an nMOS transistor and a pMOS transistor are respectively called an nMOS and a pMOS for short.
FIG. 3 shows the clock buffer 13 in detail.
The clock buffer 13 comprises a differential amplifier 19 for comparing the clock signal CLK input from the exterior with a reference voltage VREF, and a pulse generator 20 comprising an inverter and a NAND gate. The reference voltage VREF is set to a half of a supply voltage VCC (2.5V).
The differential amplifier 19 has voltage outputting parts 21 and 22 symmetric to each other and each having a pMOS and an nMOS connected in series. The gates of nM'es 21a and 22a of the voltage outputting parts 21 and 22 receive the clock signal CLK and the reference voltage VREF, respectively. The sources of the nMOS'es 21a and 22a are connected to a ground line VSS through an nMOS 23. The gate of the nMOS 23 is connected to a power supply line VCC. A node ND1 connecting the nMOS 21a to the pMOS 21b of the voltage outputting part 21 is connected to the input of the pulse generator 20.
The sources of the pMOS'es 21b and 22b are connected to the power supply line VCC. The gates of the pMOS'es 21b and 22b are connected to the drain (a node ND2) of the pMOS 22b. The voltage outputting parts 21 and 22 form a current mirror circuit.
The pulse generator 20 comprises an inverter 20a and inverter rows 20b and 20c each connecting three inverters in cascade, and a 2-input NAND gate 20d. The input of the inverter 20a is connected to the node ND1. The output of the inverter 20a is connected to one of the inputs of the NAND gate 20d and to the input of the inverter row 20b. The output of the inverter row 20b is connected to the other input of the NAND gate 20d. The output of the NAND gate 20d is connected to the input of the inverter row 20c. The output of the inverter row 20c outputs the internal clock signal CLKZ.
FIG. 4 shows the clock pulse generator 14 in detail.
The clock pulse generator 14 comprises three inverters 14a, 14b, and 14c, a flip-flop circuit 14d comprising two 2-input NAND gates, and inverter rows 14e and 14f each connecting four inverters in cascade. The input of the inverter 14a receives the internal clock signal CLKZ. The output of the inverter 14a is connected to one of the inputs of the flip-flop circuit 14d. In the flip-flop circuit 14, the output of the NAND gate which connects the inverter 14a is connected to the input of the inverter 14b. The output of the inverter 14b is connected to the input of the inverter 14c and the input of the inverter row 14e. The output of the inverter 14c outputs the clock pulse signal CEPZ. The output of the inverter row 14e is connected to the input of the inverter row 14f. The output of the inverter row 14f (a node ND3) is supplied back to the other input of the flip-flop circuit 14d.
FIG. 5 shows generation timing of the clock pulse signal CEPZ generated by the clock pulse generator 14. The clock pulse signal CEPZ rises in synchronization with a rise of the clock signal CLKZ, and falls in synchronization with a fall of a feedback signal transmitted through the node ND3. In other words, an activation period (pulse width) of the clock pulse signal CEPZ is determined by delay time of the inverter rows 14e and 14f.
FIG. 6 shows the pre-decoder 10 in detail.
The pre-decoder 10 comprises a plurality of decoding circuits 10a. Each of the decoding circuits 10a comprises a 3-input NAND gate 10b and an inverter 10c. The inputs of the NAND gate 10b receive two row address signals (for example, row address signals AZ and BZ) and the clock pulse signal CEPZ. The output of the NAND gate 10b is connected to the input of the inverter 10c. The output of the inverter 10c outputs the column decoding signal CAZ or the like.
FIG. 7 shows the main-decoder 4 in detail.
The main-decoder 4 comprises a plurality of decoding circuits 4a, as the pre-decoder 10. Each of the decoding circuits 4a comprises 3-input NAND gate 4b and an inverter 4c. The inputs of the NAND gate 4b receive three decoding signals (for example, decoding signals CAZ, CBZ and CCZ). The output of the NAND gate 4b is connected to the input of the inverter 4c. The output of the inverter 4c outputs the column selecting signals CL1Z or the like.
FIG. 8 shows the timing controlling circuit 15 in detail.
The timing controlling circuit 15 comprises six delay circuits 15a connected in cascade. Each of the delay circuits 15a comprises a CMOS inverter 15b in which the drains of a pMOS and an nMOS are serially connected to resistors R1 and R2 respectively, a MOS capacitor 15c in which the source and the drain of an nMOS are connected to the ground line VSS, and a resistor R3 connecting the output of the CMOS inverter 15b with the gate of the MOS capacitor 15c. The resistors R1, R2, and R3 are formed with diffusion layers. In other words, the delay circuit 15a is formed as a CR time constant circuit. The time constant of the delay circuit 15a is determined by a wiring load of the clock pulse signal CEPZ along the memory core unit 2, a circuit delay by the pre-decoder 10, a wiring load of the column decoding signal CAZ, and a circuit delay by the main-decoder 4, as shown in FIG. 1.
The input of the first stage delay circuit 15a receives the clock pulse signal CEPZ. The output of the second-stage delay circuit 15a outputs the write controlling signal WAEZ. The output of the final stage delay circuit 15a outputs the read controlling signal SEBZ. Activation periods of the write controlling signal WAEZ and the read controlling signal SEBZ output from the timing controlling circuit 15 are shifted by a predetermined amount of time behind an activation period of the column selecting signal CLZ, which will be explained later.
FIG. 9 shows in detail the resetting circuit 16 and peripheral circuits thereof.
The resetting circuit 16 receives the read controlling signal SEBZ, the testing signal TESZ, the read data signals RDB0Z, RDB1Z, RDB2Z, and RDB3Z, and the testing read data signals TRDBZ and TRDBX. The read data signals RDB0Z, RDB1Z, RDB2Z, and RDB3Z and the testing read data signals TRDBZ and TRDBX are signals supplied from sense buffers 8a, 8b, 8c and 8d. The sense buffers 8a, 8b, 8c, and 8d correspond to data signals DQ0, DQ1, DQ2, and DQ3, respectively. The resetting circuit 16 comprises pMOS'es 16a, 16b, 16c, 16d, 16e, and 16f for setting the read data signals RDB0Z, RDB1Z, RDB2Z, and RDB3Z, and the testing read data signals TRDBZ and TRDBX to the supply voltage VCC, inverters 16g, 16h, 16j and a 2-input NOR gate 16k controlling the pMOS'es, and a latch circuit 16m.
The input of the inverter 16g receives the read controlling signal SEBZ. The output of the inverter 16g is connected to the input of the inverter 16h and one of the inputs of the NOR gate 16k. The output of the inverter 16h is connected to the gates of the pMOS'es 16a, 16b, 16c and 16d. The other input of the NOR gate 16k receives an inverted signal of the testing signal TESZ through the inverter 16j. The output of the NOR gate 16k is connected to the gates of the pMOS'es 16e and 16f.
The latch circuit 16m comprises six latches 16n each comprising two inverters in which each one of the inputs is connected to the output of the other. Terminals of the latches 16n are respectively connected to the read data signals RDB0Z, RDB1Z, RDB2Z, and RDB3Z, and the testing read data signals TRDBZ and TRDBX. The drivability of the latches 16n is low, and data latched therein are easily inverted by operations of the pMOS'es 16a, 16b, 16c, 16d, 16e, 16f, and nMOS'es 25e, 25f, and 25g in FIG. 10 which will be explained later.
FIG. 10 shows the sense buffers 8 (8a, 8b, 8c, 8d) in detail.
The sense buffers 8 comprises a differential amplifier 24 for comparing and amplifying the internal data signals GDBZ and GDBX output from the sense amplifier 5 through the switching circuit 6, and an output circuit 25 for outputting the signals amplified by the differential amplifier 24 as the read data signal RDBZ and the testing read data signals TRDBZ and TRDBX.
The sense buffers 8 has voltage outputting parts 26 and 27 symmetric to each other and each comprising a pMOS and an nMOS connected in series. The gates of nMOS'es 26a and 27a of the voltage outputting parts 26 and 27 receive the internal data signals GDBX and GDBZ, respectively. The sources of the nMOS 26a and 27a are connected to the ground line VSS through an nMOS 28. The gate of the nMOS 28 receives the read controlling signal SEBZ. A node ND4 connecting the nMOS 26a with the pMOS 26b of the voltage outputting part 26 and a node ND5 connecting the nMOS 27a and the pMOS 27b of the voltage outputting part 27 are connected to the output circuit 25.
The sources of the pMOS'es 26b and 27b are connected to the supply line VCC. The gates of the pMOS'es 26b and 27b are connected to the node ND5. The voltage outputting parts 26 and 27 form a current mirror circuit.
The nodes ND4 and ND5 are connected to the drains of pMOS'es 29 and 30, respectively. The gates of the pMOS'es 29 and 30 receive the read controlling signal SEBZ. The sources of the pMOS'es 29 and 30 are connected to the supply line VCC.
The output circuit 25 comprises inverters 25a and 25b, two 2-input NOR gates 25c and 25d, and three nMOS'es 25e, 25f, and 25g. The input of the inverter 25a is connected to the node ND4. The output of the inverter 25a is connected to the gate of the nMOS 25e. One of the inputs of the NOR gate 25c is connected to the node ND4. One of the inputs of the NOR gate 25d is connected to the node ND5. The other inputs of the NOR gates 25 and 25d receive the inverted signal of the testing signal TESZ through the inverter 25b. The output of the NOR gate 25c is connected to the gate of the nMOS 25f. The output of the NOR gate 25d is connected to the gate of the nMOS 25g.
The drain of the nMOS 25e outputs the read data signal RDBZ. The drain of the nMOS 25f outputs the testing read data signal TRDBZ. The drain of the nMOS 25g outputs the testing read data signal TRDBX. The sources of the nMOS'es 25e, 25f, and 25g are connected to the ground line VSS.
FIG. 11 shows the write amplifier 9 in detail.
The write amplifier 9 comprises an input circuit 31 for receiving the write data signal WDBZ and the testing write data signal TWDBZ, a latch circuit 32 for latching the data received by the input circuit, and an output circuit 33 for outputting the data latched by the latch circuit 32 as the internal data signals GDBZ and GDBX.
The input circuit 31 comprises an inverter 31a and CMOS transmission gates 31b and 31c in each of which the source and the drain of a pMOS and an nMOS are connected to each other. The input of the CMOS transmission gate 31b receives the write data signal WDBZ. The input of the CMOS transmission gate 31c receives the testing write data signal TWDBZ. The outputs of the CMOS transmission gates 31b and 31c are connected to a node ND6. The PMOS gate of the CMOS transmission gate 31b and the nMOS gate of the CMOS transmission gates 31c receive the testing signal TESZ. The nMOS gate and the pMOS gate of the CMOS transmission gates 31b and 31c receive the inverted signal of the testing signal TESZ through the inverter 31a.
The latch circuit 32 comprises two inverters 32a and 32b in which each one of the inputs is connected to the output of the other. The input of the inverter 32a and the output of the inverter 32b are connected to the node ND6. The output of the inverter 32a and the input of the inverter 32b are connected to a node ND7.
The output circuit 33 comprises inverters 33a and 33b and CMOS transmission gates 33c and 33d in each of which the source and the drain of a pMOS and an nMOS are connected to each other. The input of the CMOS transmission gate 33c is connected to the node ND7 through the inverter 33a. The input of the CMOS transmission gate 33d is connected to the node ND7. The output of the CMOS transmission gate 33c outputs the internal data signal GDBZ. The output of the CMOS transmission gate 33d outputs the internal data signal GDBX. The nMOS gates of the CMOS transmission gates 33c and 33d receive the write controlling signal WAEZ. The PMOS gates of the CMOS transmission gates 33c and 33d receive an inverted signal of the write controlling signal WAEZ through the inverter 33b.
FIG. 12 shows in detail a data input circuit 34 and peripheral circuits thereof in the data input/output circuit 12.
The data input circuit 34 comprises an inverter 34a, CMOS transmission gates 34b, 34c, 34d, 34e, 34f, 34g, and 34h in each of which the source and the drain of a pMOS and an nMOS are connected to each other.
The inputs of the CMOS transmission gates 34b, 34c, 34d, and 34e receive the data signal DQ0. The output of the CMOS transmission gate 34b outputs the write data signal WDB0Z. The output of the CMOS transmission gate 34c outputs a testing write data signal TWDB1Z. The output of the CMOS transmission gate 34d outputs a testing write data signal TWDB2Z. The output of the CMOS transmission gate 34e outputs a testing write data signal TWDB3Z.
The input of the CMOS transmission gate 34f receives the data signal DQ1. The output of the CMOS transmission gate 34f outputs the write data signal WDB1Z. The input of the CMOS transmission gate 34g outputs the data signal DQ2. The output of the CMOS transmission gate 34g outputs the write data signal WDB2Z. The input of the CMOS transmission gate 34h receives the data signal DQ3. The output of the CMOS transmission gate 34h outputs the write data signal WDB3Z.
The pMOS gate of the CMOS transmission gate 34b is connected to the ground line VSS. The nMOS gate of the CMOS transmission gate 34b is connected to an internal power supply line VII. The voltage of the internal supply line VII is 2.0V. The nMOS gates of the CMOS transmission gates 34c, 34d, and 34e receive the testing signal TESZ. The PMOS gates of the CMOS transmission gates 34c, 34d, and 34e receive the inverted signal of the testing signal TESZ through the inverter 34a. The pMOS gates of the CMOS transmission gates 34f, 34g, and 34h receive the testing signal TESZ. The nMOS gates of the CMOS transmission gates 34f, 34g, and 34h receive the inverted signal of the testing signal TESZ through the inverter 34a.
The write data signal WDB0Z is also used as the testing write data signal TWDB0Z. The write data signals WDB0Z, WDB1Z, WDB2Z and WDB3Z are connected to different write amplifiers 9a, 9b, 9c and 9d, respectively. The testing write data signals TWDB0Z, TWDB1Z, TWDB2Z and TWDB3Z are connected to the different write amplifiers 9a, 9b, 9c and 9d, respectively.
In the SDRAM 1 described above, a data reading operation is carried out in the following manner.
FIG. 13 shows timings of main signals in the reading operation.
The clock pulse generator 20 in the clock buffer 13 shown in FIG. 3 generates the internal clock signal CLKZ in synchronization with a rise of the clock signal CLK [FIG. 13(a)].
By receiving the internal clock signal CLKZ, the clock pulse generator 14 shown in FIG. 4 generates the clock pulse signal CEPZ having a pulse width equivalent to the delay time caused by the inverter rows 14e and 14f [FIG. 13(b)].
The clock pulse signal CEPZ is transmitted to the pre-decoder 10, the wiring of the column decoding signal CAZ, and to the main-decoder 4 in this order, and activates the column selecting signal CLZ corresponding to a predetermined address [FIG. 13(c)]. The column selecting signal CLZ is activated lagging behind the clock pulse signal CEPZ by time T1, due to the wiring load of the lock pulse signal CEPZ, the circuit delay of the pre-decoder 10, the wiring load of the column decoding signal CAZ and the circuit delay of the main-decoder 4.
The timing controlling circuit 15 shown in FIG. 8 receives the clock pulse signal CEPZ and generates the read controlling signal SEBZ by using the delay circuit 15a [FIG. 13(d)]. The read controlling signal SEBZ is generated lagging behind the column selecting signal CLZ by time T2.
The memory cell 7 is selected by a signal and a circuit corresponding to a row address which is not shown, and the bit line signals BLZ and BLX are output from the memory cell 7 [FIG. 13(e)]. Practically, voltages of the bit line signals BLZ and BLX change by distribution of a storage charge in the memory cell 7 to the wiring of the bit line signals.
The switching circuit 6 shown in FIG. 2 is turned on by receiving the column selecting signal CLZ at high level. Signal levels of the bit line signals BLZ and BLX are transmitted as the internal data signals GDBZ and GDBX through the switching circuit 6 [FIG. 13(f)].
The resetting circuit 16 shown in FIG. 9 turns off the pMOS'es 16a, 16b, 16c and 16d by receiving the read controlling signal SEBZ at high level. The read data signal RDBZ (RDB0Z, RDB1Z, RDB2Z and RDB3Z) is retained a high level by the latch circuit 16m. Since the testing signal TESZ is at low level in a normal operation, the nMOS'es 16e and 16f are always ON.
The differential amplifier 24 in the sense buffer 8 shown in FIG. 10 accepts the internal data signals GDBZ and GDBX by receiving the read controlling signal SEBZ at high level. The differential amplifier 24 carries out differential amplification of the internal data signals GDBZ and GDBX and outputs the amplified signals to the nodes ND4 and ND5. The output circuit 25 of the sense buffer 8 receives the amplified signals and outputs the signals as read data signal RDBZ (RDB0Z, RDB1Z, RDB2Z, and RDB3Z) [FIG. 13(g)]. When the internal data signal GDBZ is at high level, the node ND4 becomes a high level. The nMOS 25e is turned off at this time and the read data signal RDBZ retains a high level. When the internal data signal GDBZ is at low level, the node ND5 is at low level. At this time, the nMOS 25e is turned on and the read data signal RDBZ is at low level. The read data signal RDBZ is supplied to the long wiring in the horizontal direction of the chip, as shown in FIG. 1. Therefore, the level of the read data signal slowly varies to the low level. By turning on the nMOS 25e', the data latched in the latch 16n shown in FIG. 9 are inverted.
By the data input/output circuit 12 shown in FIG. 2, the read data signal RDBZ is output to the pad as the data signal DQ, and the read operation is completed.
In the SDRAM 1 described above, a data writing operation is carried out in the following manner.
FIG. 14 shows timings of main signals in the write operation in the SDRAM 1. Since the timings of the clock signal CLKZ, the clock pulse signal CEPZ, and the column selecting signal CLZ are the same as in the read operation, explanation thereof is omitted.
The timing circuit 15 shown in FIG. 8 receives the clock pulse signal CEPZ and generates the write controlling signal WAEZ by using the delay circuit 15a [FIG. 14(a)]. By using the delay circuit 15a, the write controlling signal WAEZ is generated ahead of the column selecting signal CLZ by time T3.
The data input/output circuit 12 shown in FIG. 12 accepts the data signal DQ (DQ0, DQ1, DQ2, and DQ3) from the exterior. The testing signal TESZ is set at low level in a normal operation. The CMOS transmission gates 34b, 34f, 34g and 34h turn on and turn off the CMOS transmission gates 34c, 34d, and 34e turn off. Therefore, the data signals DQ0, DQ1, DQ2, and DQ3 accepted are respectively transmitted to the write amplifiers 9a, 9b, 9c, and 9das the write data signals WDB0Z, WDB1Z, WDB2Z, and WDB3Z (collectively called the write data signal WDBZ) [FIG. 14(b)].
The write amplifier 9 shown in FIG. 11 latches the accepted write data signal WDBZ by the latch circuit 32. The output circuit 33 of the write amplifier 9 outputs signals at a signal level of the node ND7 and the inverted level thereof as the internal data signals GDBX and GDBZ when the write controlling signal WAEZ is at high level [FIG. 14(c)].
The switching circuit 6 shown in FIG. 3 is turned on by receiving the column selecting signal CLZ at high level. The signal levels of the internal data signals GDBX and GDBZ are transmitted as the bit line signals BLX and BLZ through the switching circuit 6 [FIG. 14(d)].
The memory cell 7 is selected by a signal and a circuit corresponding to a row address which is not shown. The levels of the bit line signals BLZ and BLX are written to the memory cell 7, and the write operation is completed.
In the SDRAM 1 described above, data compressing test is carried out in the following manner. The shift to the compressing test mode is carried out by a command input or the like from the exterior. The testing circuit 17 shown in FIG. 1 turns the testing signal TESZ to a high level by receiving the shift to the compression mode.
A write operation in the compressing test mode will be explained first.
FIG. 15 shows timings of main signals related to the write operation.
The data input/output circuit 12 shown in FIG. 12 receives the testing signal TESZ at high level and the CMOS transmission gates 34c, 34d, and 34e is turned on while the CMOS transmission gates 34f, 34g, and 34h is turned off. The data input/output circuit 12 transmits the data signal DQ0 accepted from the exterior as the testing write data signals TWDB0Z, TWDB1Z, TWDB2Z, and TWDB3Z (collectively called the testing write data signal TWBDZ) to the write amplifiers 9a, 9b, 9c and 9d. Since the testing write data signal TWBDZ is generated only from the data signal DQ0, a waveform thereof is gentler than the waveform of the write data signals WDBZ [FIG. 15(a)].
The write amplifier 9 shown in FIG. 11 receives the testing signal TESZ at high level and turns off the CMOS transmission gates 31b while turning on the CMOS transmission gate 31c. The latch circuit 32 latches the testing write data signal TWDBZ through the CMOS transmission gate 31c. The output circuit 33 receives the write controlling signal WAEZ at high level, and outputs a signal transmitted to the node ND7 and an inverted signal thereof as the internal data signals GDBX and GDBZ [FIG. 15(b)].
As in the write operation in a normal operation, the value of the data signal DQ0 is written to each of the memory cells 7 through the forms of the bit line signals BLZ and BLX.
A data reading operation in the compressing test mode will be explained next. FIG. 16 shows timings of main signals related to the read operation in the compressing test mode.
By receiving the read controlling signal SEBZ at high level, the differential amplifier 24 in the sense buffer 8 shown in FIG. 10 accepts the internal data signals GDBZ and GDBX. The differential amplifier 24 carries out differential amplification and outputs amplified signals to the nodes ND4 and ND5. The output circuit 25 of the sense buffer 8 receives the testing signal TESZ at high level and activates the NOR gates 25c and 25d. By this activation, when the nodes ND4 and ND5 are at high level and at low level respectively, nMOS'es 25f and 25g are turned on and off respectively, while the testing read data signals TRDBZ and TRDBX are at high level and at low level respectively. When the nodes ND4 and ND5 are at low level and at high level respectively, the nMOS'es 25f and 25g are turned on and off respectively, while the testing read data signals TRDBZ and TRDBX are at low level and at high level respectively [FIG. 16(a)].
The resetting circuit 16 shown in FIG. 9 receives the testing signal TESZ at high level and turns on the PMOS'es 16e and 16f when the read controlling signal SEBZ is at low level. On the other hand, the resetting circuit 16 turns off the pMOS'es 16e and 16f when the read controlling signal SEBZ is at high level (meaning the read operation). Wiring of the testing read data signals TRDBZ and TRDBX of the sense buffers 8a, 8b, 8c, and 8d corresponding to the data signals DQ0, DQ1, DQ2 and DQ3 is shared. As has been described above, the same data have been written to the memory cells 7 each corresponding to the sense buffers 8a, 8b, 8c and 8d. Therefore, when the memory cells 7 or the like are not malfunctioning, the testing read data signals TRDBZ and TRDBX are at different levels. When the memory cells 7 or the like are malfunctioning, any one of the nMOS'es 25f or 25g of the sense buffers 8a, 8b, 8c and 8d is on. For this reason, both of the testing read data signals TRDBZ and TRDBX a low level and the malfunctioning of the memory cells 7 is detected.
Since the wiring of the testing read data signals TRDBZ and TRDBX is connected to the plurality of the sense buffers 8a, 8b, 8c and 8d, a load thereof is large. Therefore, as shown in FIG. 16, waveforms of the testing read data signals TRDBZ and TRDBX are gentler than the waveform of the read data signal RDBZ. The read operation is carried out at the same timing as the read operation timing shown in FIG. 13, except for the waveforms of the testing read data signals TRDBZ and TRDBX.
As shown in FIG. 8, the write controlling signal WAEZ and the read data signals RDBZ are generated lagging behind the column selecting signal CLZ by the predetermined amount of time, by using the delay circuits 15a combining the CR time constant circuits. Meanwhile, the activation timing of the column selecting signal CLZ is determined by the wiring load of the clock pulse signal CEPZ, the circuit delay of the pre-decoder 10, the wiring load of the column decoding signal CAZ, and the circuit delay of the main-decoder 4. Therefore, relative deviations between the activation timings of the write controlling signal WAEZ and the column selecting signal CLZ, and between the read data signals RDBZ and the column selecting signal CLZ easily fluctuate due to a change occurring in a manufacturing process, an operation voltage, and ambient temperature.
If the activation timing of the read controlling signal SEBZ is earlier than the activation timing of the column selecting signal CLZ, a problem occurs in the read operation. In other words, the sense buffer 8 shown in FIG. 10 accepts wrong data existing before the internal data signals GDBZ and GDBX are transmitted. In the sense buffer 8, the value of the read data signal RDBZ is determined by the data accepted first. Therefore, the SDRAM 1 outputs wrong data as the data signal DQ.
The problem in the read operation is caused by a narrow wiring width due to a fluctuation occurring in a manufacturing process (in photolithography process or etching process), for example. The narrower width leads to an increase in a wiring resistance, leading to a longer propagation delay time of signal. In other words, the clock pulse signal CEPZ and the column decoding signal CAZ having long total wiring lengths are affected greatly by the increase in the delay time due to the increase in the wiring resistance, and have a larger propagation delay than other signals.
The problem in the read operation also occurs in the case where the resistance of the resistors R1, R2 and R3 (diffusion resistance) used in the delay circuit 15a is decreased due to a fluctuation occurring in a manufacturing process (in ion-implantation process or heat treatment process), for example. Furthermore, the deviations between the timings are fluctuated by fluctuations occurring in the operation voltage or ambient temperature.
If the activation timing of the write controlling signal WAEZ is later than the activation timing of the column selecting signal CLZ, a problem occurs in the write operation. In other words, the switching circuit shown in FIG. 2 transmits to the sense amplifier 5 wrong data which are not proper write data from the write amplifier 9. The sense amplifier 5 amplifies the wrong data and then amplifies the proper write data from the write amplifier 9. Therefore, an access time becomes longer. In the case where the proper write data are not amplified in a write cycle, the wrong data are written to the memory cell 7.
The above problem in the write operation occurs due to reduction in wiring resistance and in diffusion resistance.
The above problem has been dealt with by increasing the time T2 shown in FIG. 13. However, if the time T2 is increased, an expected access time may not necessarily be obtained.
Especially, in the case of a chip operating at a high speed, it is necessary for timing margins of the controlling signals in the internal circuit to be set small. Furthermore, the permissible ranges of the deviations between the activation timings of the write controlling signal WAEZ and the column selecting signal CLZ and between the read data signal RDBZ and the column selecting signal CLZ need to be set as narrow as possible. For this reason, the above problem is more conspicuous.
For a chip operating at a low voltage, a delay time of a gate circuit such as an inverter changes greatly depending on a fluctuation of an operation voltage. Especially, a fluctuation of a delay time of a delay circuit combining an inverter and a CR time constant circuit tends to be large. Therefore, the above problem is more conspicuous.
Furthermore, waveform check of the column selecting signal CLZ or the like has not been carried out on a product to be shipped. A waveform of a controlling signal in an internal circuit can generally be checked by using an electron beam tester. However, this evaluation method needs to remove an insulator or the like on the chip, and is not applied to a product to be shipped. It is also possible to form an evaluating pad in advance for a controlling signal to be checked. However, molded chip cannot be evaluated by this method. Furthermore, the evaluating pad and wiring thereof are loads irrelevant to operation, which may obstructs a high-speed operation.
The SDRAM 1 described above has a further problem below.
The column selecting signal CLZ and the write controlling signal WAEZ are generated from the clock pulse signal CEPZ and have almost the same activation periods. Since the write controlling signal WAEZ is activated earlier than the column selecting signal CLZ, the column selecting signal CLZ is activated lagging behind inactivation of the write controlling signal WAEZ by the time T3, as shown in FIG. 17.
In time T4 when the write controlling signal WAEZ and the column selecting signal CLZ are both active, the difference between the levels of the bit line signals BLZ and BLX to be written to the memory cell 7 becomes larger due to the drivability of the write amplifier 9 and amplifying power of the sense amplifier 5. In the time T3 when the write controlling signal WAEZ is inactivated, the level difference between the bit line signals BLZ and BLX increases only due to the amplifying power of the sense amplifier 5. Therefore, in the time T3, the level difference between the bit line signals BLZ and BLX is gentler than in the time T4. As a result, a write voltage to the memory cell 7 is lowered, and a data retaining time of the memory cell 7 is shortened. Recently, the active time of the CLZ signal tends to be shortened due to a high-speed operation, and the level difference between the bit line signals BLZ and BLX needs to be increased in a short time.
In the compressing test mode, the following problem occurs.
As shown in FIG. 12, in the write operation, one data signal DQ is output to the write amplifier 9 as the plurality of the testing write data signals TWDB0Z, TWDB1Z, TWDB2Z, and TWDB3Z. In the read operation, as shown in FIG. 9, the wiring of the testing read data signals TRDBZ and TRDBX are connected to the plurality of the sense buffers 8a, 8b, 8c and 8d. Therefore, waveforms of the testing write data signals TWDB0Z, TWDB1Z, TWDB2Z, and TWDB3Z, and the testing read data signals TRDBZ and TRDBX become gentle due to the wiring load of each signal line and a load of the circuits connected thereto.
For example, in the read operation, as shown in FIG. 16, the activation periods of the controlling signals such as the column selecting signal CLZ and the read controlling signal SEBZ need to be set in such a manner that the low level of the testing read data signal TRDBZ takes a predetermined voltage. When only the normal operation mode is considered, timing of each signal is set to the timing which enables the read data signal RDBZ to be amplified sufficiently, as shown by dashed lines in FIG. 16. However, in the SDRAM1 described above, a high-speed operation cannot be realized regardless of a timing margin in the normal operation mode, since the timing of each signal is determined in accordance with the timings in the compressing test mode.